1. Field of the Invention
This invention is related to the field of processors and, more particularly, to resource renamers in processors.
2. Description of the Related Art
Processors form the heart of various computer systems, and are also rapidly becoming a key component in many other electronic systems. Processors execute instructions in a defined instruction set architecture, and a variety of software programs implementing the instruction set may be written to execute on the processors. Thus, processors offer flexibility in the system operation and usefulness.
Processors implement a variety of microarchitectural features in an attempt to increase the performance of instruction execution. Some processors permit out of order instruction execution, in which instructions that are ready to execute (e.g. all of their operands are ready) are permitted to execute even if older instructions are not yet ready to execute. Improvement in overall instruction execution rates may be achievable using out of order instruction execution.
One complication in out of order instruction execution is the write after read hazard. That is, if an older instruction reads a register (or other resource) and a younger instruction writes that same register, the older instruction must read the register before the younger instruction writes the register. Similarly, a write after write hazard exists if an older instruction and a younger instruction both write the same register. The older instruction's write must occur first.
Register renaming assigns temporary register locations to each register-writing instruction. If the instruction executes out of order with older instructions that read the same register, the instruction writes the temporary register and thus does not destroy the preceding value. As instructions are processed through the register renamer, the register addresses in the instructions are replaced with the current “rename” addresses identifying the temporary registers. Additionally, the renamer is updated with newly assigned renames for the instructions being processed. Accordingly, the renamer maintains a mapping of registers to renames.
Maintaining the rename mapping as instructions are retired (and their results committed) is a complicated process. Typically, an indication of the retired instruction must be compared to the renamer state to identify which, if any, rename mapping is invalidated (and the actual architected register is used instead). A content addressable memory (CAM) may be used for this purpose. If more than one instruction can be retired at the same time, additional CAM ports are required for each retiring instruction. Additionally, standard CAM memory comparisons typically consume significant power.